In the past, there were package boards employed for an electrical connection between a device manufactured in a wafer process and external circuitry or apparatus to effect transmission of signals from the device, as well as supply of external power to the device. Package boards employed in the past included, as shown in FIG. 1, a diced piece of IC chip 101 mounted on a board 103 greater than the IC chip and formed with a re-wiring layer 102, with connections, such as by gold wires 104, between the IC chip 101 and the re-wiring layer 102.
Moreover, in the past, there was employed also a package system in which, as shown in FIG. 2, a bare chip IC 101 having metal bumps 105 formed thereon was implemented on a board formed with a re-wiring layer 102, using an anisotropic conductive adhesive 106.
However, along with functional multiplication in recent mobile electronics, semiconductor devices also have faced needs for additional miniaturization, most of which have been focused on miniaturization of a package, rather than high integration of ICs.
Recent years have observed development of a wafer-level chip-scale package (referred herein to “WLCSP”) as an ultimate miniature package made simply by a build-up method. As shown in FIG. 3, the WLCSP has a direct wiring (re-wiring layer 102) formed by a build-up method, on an IC 101, using a silicon wafer 101 as a base, and is a minimal package having a package size equal to a chip size.
However, the number of terminals to be arranged on a package is limited by a rule on the terminal pitch of boards to be implemented, and the application of WLCSP is restricted to such devices that have a small number of pins. As a technique for expansion against such a restricted situation of WLCSP, there has been proposed a chip built-in board. For the chip built-in board, an IC chip mounted on a board has a re-wiring layer built simply by build-up techniques.
Like the above-noted chip built-in board, there are core-less wiring boards to be formed simply by a build-up method, which are well-suited as boards for connection of such devices that have fine wirings fabricated by a technique of wafer process. However, the fabrication process costs very high in comparison with a typical printed board, i.e., such one that has circuits fabricated by etching copper foils and multi-layered by adhesion. Further, the chip built-in board has as many processes as the number of necessary wiring layers, to be executed in series, requiring a long term for fabrication, and the yield also has a decreasing tendency, as it corresponds to as much accumulation as the number of processes.
Further, for multi-layer boards using polyimide as bases and multi-layered by stacking their wirings, although it is possible to make highly defined wirings in a layer, the connection between layers depends on a mechanical positioning precision. In such a multi-layer board, therefore, the interlayer connection needs a design in consideration of alignment errors between layers, with a resultant restriction to the pitch of vias (plugging electrodes).